1. Technical Field
The present invention relates to a semiconductor device having a semiconductor element packaged therein, and a method of manufacturing the same.
2. Related Art
Minimization of influences of parasitic capacitance may be an effective means for improving performances of transistors. For this purpose, various techniques of reducing the parasitic capacitance, based on covering an active region of a chip using a material having a lower dielectric constant, have been proposed.
For example, a semiconductor device described in Japanese Laid-Open Patent Publication No. H8-070061 has, on an integrated circuit substrate having a semiconductor element mounted thereon, a micro wall of a certain height, risen up on the integrated circuit substrate in the normal direction so as to surround the semiconductor element. The micro wall is composed of an insulating material, electroconductive material, or the like. Space surrounded by the micro wall is closed by a micro lid, so as to form a cavity therein. The micro lid is composed of an electroconductive material.
Japanese Laid-Open Patent Publication No. H8-070061 describes that the above-described configuration allows protection of the semiconductor elements without causing degradation in electrical characteristics of the integrated circuit, because a resin used for encapsulation by potting will never be brought into contact with the semiconductor element and signal lines in the cavity, and that high-frequency integrated circuit may be obtained at low costs.
However, the conventional technique described in Japanese Laid-Open Patent Publication No. H8-070061 still had a room of improvement in the aspects below.
First, the micro lid and micro wall, containing an electroconductive material, may possibly be brought into contact with wire provided so as to contact with electrode pads on the element, to thereby cause electrical short circuiting.
Second, the micro wall and the micro lid have occasionally resulted in separation at the joint portion, if they had different values of linear coefficient of expansion. The molding resin may therefore enter the space, and may give damage to the active region.
Third, the active region has occasionally cause physical or chemical damage when the micro lid is fixed to the top of the micro wall by methods of bonding such as soldering, heat cladding, ultrasonic cladding and welding, and thereby yield ratio of products has occasionally degraded.